FPGA-Based Radio Signal Digital Processing Systems Engineer

İş haqqında

Developing FPGA-based digital radio signal processing modules in hardware description languages (VHDL, Verilog, SystemVerilog);Implementing and porting DSP algorithms (filtering, modulation/demodulation, error-correcting coding) from mathematical models (MATLAB/Simulink) to FPGA architecture;Designing interfaces between FPGAs and high-speed ADCs/DACs and external buses (PCIe, JESD204B/C, DDR3/DDR4, etc.);Functional verification of developed blocks: writing testbenches, simulation in ModelSim/QuestaSim;Synthesis, placement and routing of the design, optimization for timing and FPGA resource usage;Debugging the design on hardware test benches using embedded logic analyzers (ChipScope/Signal Tap, Identify);Developing accompanying technical documentation for the developed modules. Əsas vəzifələr Developing FPGA-based digital radio signal processing modules in hardware description languages (VHDL, Verilog, SystemVerilog); Implementing and porting DSP algorithms (filtering, modulation/demodulation, error-correcting coding) from mathematical models (MATLAB/Simulink) to FPGA architecture; Designing interfaces between FPGAs and high-speed ADCs/DACs and external buses (PCIe, JESD204B/C, DDR3/DDR4, etc.); Functional verification of developed blocks: writing testbenches, simulation in ModelSim/QuestaSim; Synthesis, placement and routing of the design, optimization for timing and FPGA resource usage; Debugging the design on hardware test benches using embedded logic analyzers (ChipScope/Signal Tap, Identify); Developing accompanying technical documentation for the developed modules. Tələblər Higher technical education (radio engineering, communication systems, automation, applied mathematics or a related field); 1–2+ years of experience developing FPGA-based digital devices in VHDL and/or Verilog/SystemVerilog; Knowledge of the fundamentals of digital signal processing (DSP) and digital circuit design; Experience in functional verification (writing testbenches, working with ModelSim/QuestaSim simulators); Experience with FPGA vendor CAD tools (Xilinx Vivado/ISE, Intel/Altera Quartus); Understanding of the principles of synthesis and optimization of designs for timing and resource utilization; Ability to read technical documentation, including in English.